The present invention relates to an interruption control technique in a data processing system having a plurality of central processing units and an accelerator and, for example, relates to a technique effectively applied to a system-on-chip semiconductor integrated circuit.
In a data processing system, to lessen the burden on a central processing unit (also simply described as CPU), an accelerator for performing specific data processes such as image recognition and coding/decoding of image data is mounted, and a sub-CPU to lessen the burden with respect to control on the accelerator is also mounted, thereby improving the performance as a whole. The interruption control in the multiple CPU has the following modes.
In a first mode, in the case where the accelerator can issue an interrupt request signal only to an interrupt controller on the main CPU side, to interrupt the sub-CPU by the accelerator, the accelerator has to interrupt the main CPU and cause interruption in the sub-CPU, use an interrupt routine of the main CPU, and interrupt the sub-CPU. On the other hand, in the case where the accelerator can issue an interrupt request signal only to an interrupt controller on the sub-CPU side, to interrupt the main CPU, the accelerator has to interrupt the sub-CPU and cause interruption in the main CPU by using an interrupt routine of the sub-CPU.
In a second mode, an interrupt mask register corresponding to each CPU is prepared, and only the interrupt mask corresponding to a CPU to be interrupted is cancelled by software. Even if the accelerator issues an interruption to all of the CPUs, only the CPU whose mask is cancelled is interrupted. Japanese Unexamined Patent Publication No. Sho 63 (1988)-163656 discloses a technique called a floating interrupt mechanism as an interrupt control technique classified to the second mode.
As a third mode, an interrupt priority corresponding to each CPU is set, and the accelerator issues an interrupt to all of the CPUs. When an interrupt is issued, the CPU determines whether or not it should receive the interrupt or not on the basis of its interrupt priority. At the time point when one CPU accepts the interrupt, acceptance of the interrupt by the other CPUs is masked.